Skip to content

Artificial Intelligence

Co-Packaged 1.6-Tbps Silicon Photonics Switches Cut MoE All-to-All Dispatch Tail Latency by 58 Percent Across 1,024-GPU Clusters

Santa Clara and San Jose optical-interconnect architects integrate microring-modulator optical engines directly onto 51.2-Tbps radix switch substrates with dynamic wavelength routing.

By Lazy Tensor
Published · 2 min read

Optical-interconnect engineers in a Santa Clara lab inspecting a 1.6-Terabit co-packaged silicon photonics switch ASIC with fiber-optic ribbons and eye-diagram oscilloscopes
Optical-interconnect engineers at a Santa Clara photonics lab inspect a 51.2-Tbps co-packaged optics (CPO) switch substrate surrounded by polarization-maintaining single-mode fiber ribbons.
Your listening Queue & catch up
Unheard stories first, timed at 1×. Your selections stay first.

Add a story or build a catch-up queue to start listening.

Silicon-photonics architects and distributed-training networking engineers across Santa Clara, San Jose, and Stanford University published production fabric telemetry on Saturday evening through the Optical Internetworking Forum (OIF) Co-Packaged Optics working committee, demonstrating that 51.2-Terabit-per-second (Tbps) radix switches equipped with 1.6-Tbps co-packaged silicon photonics (CPO) optical engines reduce Mixture-of-Experts (MoE) AllToAll token-dispatch 99th-percentile tail latency by 58 percent and cut interconnect wall-plug power by 62 percent across 1,024-GPU training clusters. As sparse frontier models scale to 64 or 128 routed experts per layer with top-4 token routing, electrical copper flyover cables and pluggable OSFP transceivers consume more than 30 watts per port in DSP retiming power and suffer frequent link-flap retransmissions.

In the validated CPO package architecture, thirty-two 1.6-Tbps silicon-photonic chiplets are flip-chip bonded directly onto the organic substrate surrounding the central 51.2-Tbps CMOS packet-switch ASIC, shrinking the electrical SerDes trace length from 280 millimeters to less than 9 millimeters. Eliminating the external pluggable retimer DSP lowers port-to-port serialization latency from 115 nanoseconds to 14 nanoseconds while reducing optical energy consumption to 4.1 picojoules per bit driven by external field-replaceable continuous-wave (CW) 8-wavelength DFB laser modules.

To prevent congestion collapse when skewed expert routing concentrates micro-bursts onto hot destination ranks, the switch ASIC implements credit-scheduled adaptive packet spraying across a flat two-tier Dragonfly+ topology. Nanosecond-scale wavelength-selective circuit reconfiguration dynamically reallocates optical lambdas toward oversubscribed expert groups during each forward and backward dispatch barrier.

Tested on a 1,024-accelerator MoE training cluster at 2400 Condensa Street in Santa Clara funded through a $520,000 ARPA-E LIGHTS photonics research grant, step-level communication exposure dropped from 31 percent to 12.8 percent of total iteration time. Open optical link-budget simulators and RoCEv2 adaptive-routing patches are available in the Open Compute Project Networking Repository.

Sources

Comments (0)

No comments yet. Be the first to share a thought on this story.

Lazy Tensor briefing

The ideas shaping technology and capital.

Independent reporting and analysis on the investors, companies, and technologies shaping tomorrow’s economy.

Subscribe to Lazy Tensor

Free to read. Unsubscribe anytime.

More from Lazy Tensor