Co-Packaged Silicon Photonics Interconnects Cut Multi-Rack All-Reduce Latency by 62% at 1.6 Tbps per Port

Optical interconnect engineers and datacenter systems researchers across San Jose, Santa Clara, and UC Berkeley published hardware characterization results on Friday morning through the Open Compute Project High-Performance Computing sub-committee, demonstrating a 1.6-terabit-per-second Co-Packaged Optics (CPO) silicon photonics engine mounted directly onto an AI accelerator organic substrate alongside High-Bandwidth Memory (HBM) stacks. In conventional multi-rack GPU clusters, electrical SerDes signals traveling more than two meters across printed circuit boards and copper twinax cables require power-hungry digital signal processor (DSP) retimers that consume up to 22 watts per 800-gigabit port. By converting electrical bitstreams into sixteen continuous-wave laser wavelengths inside the accelerator package itself, the monolithic silicon microring modulator array drives single-mode optical fibers up to 500 meters at just 3.8 picojoules per bit.

Across a 256-accelerator testbed executing ring and tree Collective All-Reduce operations for tensor-parallel and expert-parallel Mixture-of-Experts (MoE) layers, the retimer-free optical fabric reduced small-message synchronization tail latency by 62 percent and improved end-to-end token throughput by 28 percent on 128,000-context training runs. Eliminating electrical SerDes equalization stages also enabled a flat optical circuit switch (OCS) topology negotiated in microseconds by SONiC Open Network Software control planes.

To address field serviceability concerns that historically slowed datacenter optics adoption, the engineering consortium separated the thermally sensitive indium-phosphide Continuous-Wave laser sources into hot-swappable External Laser Small Form-Factor Pluggable (ELSFP) front-panel modules. If a laser diode degrades after years of continuous operation, datacenter technicians can swap the front-panel light source in thirty seconds without disturbing the liquid-cooled cold plate or accelerator socket.

Full thermal-cycling reliability curves, bit-error-rate eye diagrams below 1e-15 pre-FEC, and open mechanical socket drawings have been contributed to the OCP Optical Interconnect specification repository. Systems architects can review the testbed telemetry and reference board schematics via the Open Compute Project Technical Library.