Co-Packaged Silicon Photonics Interposers Deliver 16 Tbps Bi-Directional Escape Bandwidth at 1.9 Picojoules per Bit Across Multi-Rack Clusters

Optical interconnect architects and packaging engineers across Santa Clara, San Jose, and the UC Berkeley Marvell Nanofabrication Laboratory published multi-rack link-error benchmarks on Saturday afternoon through the Optical Internetworking Forum (OIF) Co-Packaged Optics technical committee, demonstrating a Co-Packaged Silicon Photonics Interposer that sustains 16 terabits per second (Tbps) of bi-directional escape bandwidth per accelerator socket at an end-to-end energy efficiency of 1.9 picojoules per bit. As frontier mixture-of-experts (MoE) training and low-latency decode clusters scale all-to-all collective domains beyond 576 GPUs across multiple rows of liquid-cooled racks, traditional copper flyover cables and pluggable 1.6T OSFP transceivers encounter severe reach limits and consume up to 24 picojoules per bit in SerDes retimer overhead.

The newly validated package architecture mounts eight 2-Tbps 3D photonic-electronic engine chiplets directly onto the organic substrate perimeter surrounding dual compute dies and twelve HBM4 memory stacks. Each photonic engine employs a dense wavelength-division multiplexing (DWDM) comb of 64 continuous-wave wavelengths fed by field-replaceable external laser small-form-factor pluggable (ELSFP) modules on the server faceplate, keeping heat-sensitive III-V laser diodes away from the 85-degree Celsius processor thermal zone.

By driving silicon micro-ring resonator modulators directly from 5-nanometer companion CMOS driver chiplets across 35-micron copper micro-bumps, electrical trace length shrinks from 280 millimeters to under 4 millimeters. Across a 150-meter single-mode fiber fabric linking sixteen racks at 2850 Junction Avenue in San Jose, raw pre-FEC bit error rates remained below 1e-9 with only 14 nanoseconds of serialization and time-of-flight overhead.

The $420,000 open multi-vendor interposer testbed program releases mechanical fiber-array blind-mate connector tolerances and thermal-wavelength locking firmware to member labs. Hardware engineers can download the optical link budget specifications on the Optical Internetworking Forum Implementation Portal.