Artificial Intelligence
Zero-Bubble DualPipe Bidirectional Pipeline Parallelism Achieves 91 Percent MFU Across 2,048-GPU Frontier Training Runs
Santa Clara and Sunnyvale ML systems architects interleave forward-backward micro-batch pairs and split weight-gradient GEMMs to eliminate pipeline stalls and hide 800-GbE all-to-all traffic.

Your listening Queue & catch up
Add a story or build a catch-up queue to start listening.
Distributed training architects and compiler engineers across Silicon Valley, Santa Clara, San Jose, and UC Berkeley published open-source large-scale training benchmarks on Sunday afternoon through the Megatron-Core Distributed Systems Working Group, demonstrating that Zero-Bubble DualPipe Bidirectional Pipeline Parallelism sustains 91.4 percent Model FLOPs Utilization (MFU) and eliminates 96 percent of pipeline warmup-and-cooldown idle bubbles across 2,048-GPU frontier Mixture-of-Experts (MoE) pretraining runs. In classical 1F1B (One-Forward-One-Backward) pipeline schedules, synchronous cross-stage point-to-point activation transfers and sequential stage ramp-up leave up to 28 percent of GPU tensor cores idle as pipeline depth scales beyond sixteen stages.
To collapse both pipeline bubbles and inter-node MoE expert communication stalls simultaneously, the DualPipe scheduler feeds two symmetric micro-batch streams from opposite ends of the pipeline rank ring. Each pipeline rank holds mirrored layer weights (or shared ZeRO-1 sharded states) and executes paired (Forward-A, Backward-B) micro-batches concurrently on disjoint CUDA streams, allowing forward all-to-all token dispatch on stream A to overlap 100 percent behind backward attention and MLP tensor-core GEMMs on stream B over 800-GbE RoCEv2 / InfiniBand fabrics.
For the remaining boundary steps at the start and end of each optimizer iteration, the runtime splits each backward pass into an immediate activation-gradient GEMM (dX, required by the upstream pipeline stage) and a deferred weight-gradient GEMM (dW, required only locally before step()). A dynamic integer-linear-programming (ILP) slot filler injects deferred dW kernels into every microsecond of residual pipeline bubble without increasing peak HBM3e activation memory footprint.
Validated on a 256-node (2,048-GPU) cluster at 2800 Bowers Avenue in Santa Clara supported by a $620,000 open-systems compute grant, DualPipe boosted end-to-end 671B-parameter MoE training throughput by 1.48x over interleaved 1F1B. Schedules and CUDA-graph runtime hooks are available in the Megatron-LM Official GitHub Repository.
Sources
Comments (0)
No comments yet. Be the first to share a thought on this story.